1. Field of the Invention
Embodiments of the present invention relate generally to graphics processing and, more specifically, to barrier commands in a cache tiling architecture.
2. Description of the Related Art
Some graphics subsystems implement a tiling architecture that divides a render target into partitions referred to as tiles. Such graphics subsystems rearrange work provided to the graphics subsystem so that work associated with any particular tile remains in an on-chip cache for a longer time than with an architecture that does not rearrange work in this manner. This rearrangement helps to improve memory bandwidth as compared with a non-tiling architecture. Multiple processing entities may be provided to process the tiles in parallel for improved performance.
Oftentimes, work executing in a graphics pipeline includes a first batch of work that is dependent on the results of a second batch of work. In such a case, if the graphics pipeline were to begin processing the first batch of work before the second batch of work is fully processed, then the results of the first batch of work would not be accurate. Among other things, those results would not be properly based on the final results from the second batch of work. In such situations, the graphics pipeline needs to be configured to honor these data dependencies.
In one traditional approach to managing data dependencies between multiple batches of work, a first batch of work is processed and all other work is stalled. When the first batch of work is completed, the other work is resumed. However, this approach incurs a large performance penalty because no work other than the work being processed may proceed. Managing data dependencies is made more complicated by a graphics architecture includes multiple processing entities operating in parallel because the data dependencies can exist across the multiple processing entities. For example, work to be processed in a first processing entity may be dependent on work being processed by a second processing entity.
As the foregoing illustrates, what is needed in the art is a technique for managing data dependencies in a tiling architecture that includes multiple processing entities that process work related to the different tiles in parallel.